1. Field of the Invention
This invention relates to a dynamic semiconductor memory device, and more particularly to a dynamic semiconductor memory device in which the interference noises between bit lines is suppressed.
2. Description of the Related Art
In recent years, the size of each memory cell is reduced and the interval between the bit lines is made shorter as the integration capacity of the semiconductor memory device becomes larger. As a result, readout noises due to the capacitive coupling between the bit lines become so large that they cannot be neglected. This problem is explained with reference to the accompanying drawings.
FIG. 1 shows an example of an arrangement of a dynamic semiconductor memory device of folded bit line configuration, BL denotes a bit line, WL denotes a word line, M denotes a memory cell, and SA denotes a sense amplifier. A case wherein the word line WL1 in FIG. 1 is selected is explained below.
FIG. 2 is a diagram showing a case where much attention is paid only to the word line WL1 in FIG. 1. When WL1 is selected, data of selected memory cells M are transferred to bit lines and the potentials of BL0m, BL3m (m =- - - , n-1, n, n+1, - - - ) are changed by a signal voltage amplitude of +Vs or -Vs according to data of "1" or "0".
The bit lines give a small potential deviation to adjacent bit lines by the capacitive coupling between bit lines and the magnitude thereof is Vs.times.CBB/CB. CBB is a coupling capacitance between the adjacent two bit lines and CB is a capacitance of the bit line to the ground.
Assume now that "1" is stored in the memory cell M0n, "1" is stored in the memory cell M3n, and "0" is stored in the memory cell M3 (n-1). In this case, since data of M0n is "1" and the potential of the bit line BL3 (n-1) is changed by -Vs, the potential of the bit line BL0n is changed by a combination of the signal and noise by an amount expressed as follows. EQU dV(BL0n)=Vs-Vs.times.CBB/CB
Further, since the potential of the adjacent bit line BL3n is changed by +Vs, the potential of BL2n which is a reference bit line of the bit line BL0n is changed by an amount expressed as follows. EQU dV(BL2n)=+Vs.times.CBB/CB
Therefore, the potential difference between BL0n and BL2n can be derived as follows. EQU dV(BL0n)-dV(BL2n)=Vs-2Vs.times.CBB/CB
The second term of the above equation indicates a noise component by the capacitive coupling between the bit lines. The above equation indicates that the relative value of noise to the unit signal becomes 2CBB/CB.
Therefore, in the dynamic semiconductor memory device shown in FIG. 1, the ratio of the noise to the signal is set to 2CBB/CB by the capacitive coupling between the bit lines, thereby causing the operation margin of a circuit such as a sense amplifier to be reduced.
On the other hand, as the pitch of the bit lines becomes smaller, the pitch of sense amplifiers also becomes smaller, and therefore, a method for sharing a sense amplifier with a plurality of bit line pairs so as to increase the pitch of the sense amplifier sections is proposed. Thereby, deceasing the area occupied by the sense amplifier on a chip surface, a total chip area becomes smaller. However, in this method, since the timings at which data is written into adjacent bit lines are different, data on the bit lines which has been written first is influenced by noise caused by a variation in the potential amplitude of the adjacent bit line into which data is written later than above bit lines.
The problem is explained with reference to the drawing. FIG. 3 shows a dynamic semiconductor memory device of folded bit line configuration in which one sense amplifier is commonly used by four bit lines and every two of them are combined to make a bit line pair. In the drawing, BL indicates a bit line, WL indicates a word line, C indicates a memory cell, SA indicates a sense amplifier, and P1, P2 indicate control signal lines for connecting the bit lines BL to the sense amplifier SA alternatively.
FIG. 4 is an operation waveform diagram in the writing operation for memory cells C0n and C1n when a word line WL1 is selected. Before starting the writing operation, the bit line BL is precharged to a middle potential Vcc/2 between two writing potentials of "1" and "0" to be set into the memory cell C, that is, vcc and 0 V. The sense amplifier SA is activated twice according to data of the memory cells C0n and C1n, connection gates between the bit lines BL and the sense amplifier SA are selected in an order of at first P1 and then P2, and so data are written into the bit lines in an order of the memory cells C0n and C1n.
FIG. 5 is a waveform diagram in the writing operation for memory cells C2n and C3n when a word line WL2 is selected in the above dynamic semiconductor memory device. Like the case of FIG. 4, the connection gates between the bit lines BL and the sense amplifier SA are selected in an order of P1 and P2, and so data are written in an order of the memory cells C2n and C3n.
In the case of FIG. 5 in which the word line WL2 is selected, data is first written into the memory cell C2n and then data is written into the memory cell C3n connected to the bit line BL3n. The bit lines BL3n and BL1n make a bit line pair and are both arranged adjacent to the bit line BL2n which is connected to the memory cell C2n. After the data of the memory cell C2n is written on the bit line BL2n, BL2n is isolated from the sense amplifier and set in the electrically floating state. After that, the data of the memory cell C3n is written on the bit line BL3n, when the complementary data is written on the reference bit line BL1n. The potential of the bit lines BL1n and BL3n varies from the precharge potential Vcc/2 to 0 V and Vcc/2 to Vcc, and the signs thereof are different and the absolute values thereof are Vcc/2, which are equal to each other. Therefore, the amount of influences on BL2n by its adjacent bit lines' voltage swing via capacitive coupling between bit lines is Just canceled because the influence of BL3n to BL2n and the influence of BL1n to BL2n have same absolute value and opposite sign. The data of the memory cell C3n, which is written on the bit line BL3n has no noise because it is activated later than BL2n. Therefore, in this case, noises caused by the capacitive coupling between the bit lines can be cancelled in the writing operation for the memory cells C2n and C3n.
However, in the case of FIG. 4 in which the word line WL1 is selected, the writing operation for the memory cell C0n connected to the bit line BL0n is first effected while the gate control signal P1 is activated. Then the control signal P1 is de-activated to set the bit line BL0n into the electrically floating state. After that, the second control signal P2 is activated and the writing operation for the memory cell C1n which is connected to the bit line BL1n is effected. At this time, the voltage potential of the bit line BL1n varies from the precharge level Vcc/2 to the signal level Vcc or 0 V, while that of the reference bit line BL3n varies complementary to BL1n. In this case, differently from the case of FIG. 5, the formerly written bit line BL0n is not arranged between the later pair of bit lines, so the potential level of BL0n can be affected by the voltage swing of the BL1n and BL3 (n-1) through the capacitive coupling between bit lines. The magnitude of this influence on the BL0n's voltage deviation is 2.times.(Vcc/2).times.CBB/CB since the absolute value of the voltage swing of an adjacent bit line is Vcc/2, the coupling ratio between the bit lines is CBB/CB and the influence comes from both sides of the bit line BL0n, from BL1n and from BL3(n-1), in the worst case.
Therefore, since written data is lost by 2CBB/CB in a relative value to a unit signal in the worst case, the amount of a signal at the time of reading is lowered by a corresponding amount. A lowering in the amount of signal at the time of reading of data causes the operation margin of the sense amplifier to be reduced. The writing noise is not present in a system in which one sense amplifier SA is. not commonly used by a plurality of bit lines and all of the bit line pairs are simultaneously activated.
The high integration density of the dynamic semiconductor memory device (DRAM) has been realized by miniaturization by the process technology and device technology, but in recent years, the miniaturization by the above technologies is coming to the upper limit. Therefore, recently, a NAND type DRAM having a NAND cell constructed by serially connecting a plurality of one-transistor/one-capacitor memory cells as a basic structure is proposed.
In the NAND type DRAM, when data is read out from a memory cell disposed at the farthest position from the bit line, the readout operation cannot be effected until data is read out from all of the cells lying closer to the bit line than the above cell, and therefore, the NAND type DRAM is inferior to the general DRAM in the access speed and the degree of freedom of access. However, since the number of contacts between the memory cells and the bit lines is reduced and consequently the area for one bit is significantly reduced, it has an extremely excellent feature in the high integration density per area and is suitable for memory devices of ultra high scale integration.
FIGS. 6 and 7 show the main portions of arrangement of a dummy cell and memory cell of the NAND type DRAM. In this example, four memory cells connected to word lines WL1 to WL4, WL5 to WL8, - - - are serially connected to construct a NAND cell. A memory cell is arranged at each intersection between the word line (WL) and the bit line (BL). The bit line BL1 on the memory cell side of FIG. 7 is connected to BL1 on the dummy cell side of FIG. 6 to make a pair, and in the same manner, BL2 and BL2, - - - make a pair so as to provide an open bit line configuration.
Each bit line is connected to a sense node (SNi) via a transfer gate (Qj). A pair of sense nodes (SNi, SNi) are connected to a sense amplifier (SAi). To the sense node, an equalizing circuit (EQZi), I/O circuit (IOGi) and 8-bit register (RGk) are connected. Each bit line pair is connected sequentially to sense amplifier by activating the transfer gates one after another.
Since the NAND type DRAM is inferior to the general DRAM in the access speed and the degree of freedom of the access because of its structure, serious deterioration in the performance will not occur even if the sense amplifier is commonly used by a plurality of bit lines in a time-sharing fashion. But it is preferable to enhance the integration density by reducing the total number of sense amplifiers in above way.
The readout operation of the NAND type DRAM of FIGS. 6 and 7 is explained below with reference to the operation waveform of FIGS. 8A and 8B. In this example, it is assumed that memory cells connected to the word lines WL1 to WL4 are selected.
First, as shown in FIG. 8A, a signal EQ is set to a high voltage, the equalizing circuit EQZi is activated, and the potentials of the sense nodes SNi and SNi are equalized and set to a previously determined voltage (for example, intermediate voltage between the power supply voltages and the ground level). At this time, the bit line selection signals BSL1 to BSL4 are set at a high voltage, the transfer gates Q1 to Q16 are set in the conductive state and the potentials of the bit lines BL1 to BL8 and BL1 to BL8 are equalized and set to the same voltage level. After the voltage equalization is completed, the potentials of BSL1 to BSL4 are set to a low level and the transfer gates Q1 to Q16 are set to be nonconductive. Further, the potential of EQ is set to a low level and the equalizing circuit EQZi is also de-activated.
Next, the potential of the first word line WL1 is set to a high voltage level, data are read out from the memory cells MC connected to WL1 and supplied to corresponding bit lines BL1 to BL8. At this time, the potential of the dummy word line DWL1 is also set to a high voltage level and reference data is read out from the dummy cell DMC connected to the above dummy word line to corresponding bit lines/BL1 to/BL8.
Then the potential of the bit line selection signal BSL1 is set to a high voltage level while the potentials of WL1 and DWL1 are kept at the high voltage level, and consequently the transistors Q1 and Q9 are made conductive to connect the paired bit lines BL1, BL1 to the paired sense nodes SN1, SN1. After data is transferred from the bit line BL1 to the sense node SN1, the potential of BSL1 is set to a low voltage level and the transistors Q1 and Q9 are made nonconductive.
After this, the sense amplifier SA1 is activated, and data which is transferred from the memory cell to the sense node SN1 through the bit line BL1 is sensed and amplified. The amplified data is input to a first bit of register lying in one of the 8-bit registers RG1 and RG2 connected to the sense nodes SN1 and SN1. At the same time, CSL1 which is an output signal of a column decoder (not shown) is set to a high voltage level and data is output to I/O line (I/O,/I/O).
After data is output to the register and I/O line, the sense amplifier SA1 is de-activated, the signal EQ is set to a high voltage level, and the equalizing circuit is operated again to equalize the potentials of the sense nodes SN1 and SN1. At this time, since the transfer gates Q1 to Q16 are kept nonconductive, data read out from the cells and dummy cells are held on the bit lines BL1 to BL8 and BL1 to B, L8. When the voltage equalization is completed, the signal EQ returns to a low voltage level and the equalizing operation ends.
Next, the second bit line selection signal BSL2 is set to a high voltage level, the transistors Q2, Q10 are set into the conductive state, the bit line BL2 is connected to the sense node SN1 and data on the bit line BL2 is transferred to the sense node SN1. After this, the transistors Q2, Q10 are set into the nonconductive state. Then, like the former case, data from the bit line BL2 is sensed and amplified at sense nodes SN1 and SN1, input to the second bit of the register, and output to the I/O line.
In succession, data of the bit lines BL3 and BL4 are sequentially read out, input to the third and fourth bits of the register, and output to the I/O line all the same way.
After data is read out from cells of four bits connected to the word line WL1 the potentials of all the bit lines and sense nodes are equalized. The potential of the word line WL2 is set to a high voltage level with the potential of the word line WL1 kept at the high voltage level as shown in FIG. 8B. Then, like the case of the word line WL1, data of cells of four bits connected to the word line WL2 are read out, input to the fifth to eighth bits of the register and output to the I/O line sequentially.
The same operation is repeatedly effected for the word lines WL3 and WL4, data of cells of 16 bits in total are read out, the readout data is held in the register and transferred to the I/O line. At this time, the same operation is simultaneously effected for the bit lines BL5 to BL8, and if SL2 is selected by the column decoder and set to a high voltage level, data is output to the I/O line, and if it is not selected, only the operation of holding data in the registers RG3 and RG4 is effected.
Next, the operation of re-writing data into the cell is effected. The re-writing operation is effected in a reverse order of the readout operation. At the time of completion of the readout operation, all of the potentials of the word lines WL1 to WL4 are set at the high voltage level. First, the bit line selection signal BSL4 is set to a high voltage level to transfer the sixteenth data from the register to a cell arranged at the intersection between the bit line BL4 and the word line WL4 through the sense node SN1.
After the writing operation of sixteenth data to its original memory cell from which it has been read out in the reading operation, the bit line selection signal BSL4 is set to a low voltage level, and instead, BSL3 is set to a high voltage level and the operation for rewriting the fifteenth data from the register into a memory cell arranged at the intersection between the bit line BL3 and the word line WL4 is effected. The same operation is repeatedly effected for fourteenth and thirteenth data, and when the re-writing operation for four cells connected to the word line WL4 is completed, the potential of the word line WL4 is set to a low voltage level to enclose data into each memory cell.
The operation similar to the above operation is repeatedly effected for wordlines WL3, WL2 and WL1, and when the operation of re-writing the first bit data into a cell disposed at the intersection between the bit line BL1 and the word line WL1 is finally effected, one operation cycle is completed. The operation of writing data from outside of the memory chip can be effected by inputting data via the I/O line, to the sense node SN1 and SN1, for example, and then effecting the same procedure as that in the re-writing operation.
As described above, the NAND type DRAM is effective as a dynamic memory device of high integration density although the degree of freedom of access is limited to some extent.
However, the conventional NAND type DRAM shown in FIGS. 6 and 7 is inferior in the noise problem that it tends to be influenced by the interference noise between the bit lines as described below. The interference noise between the bit lines is explained by mainly using the memory cell MC4 with reference to FIG. 9.
First, at the time of reading, the potential of the word line WL1 is set at the high voltage level and changes in the memory cells MC1 to MC8 are transferred to corresponding bit lines. At this time, the bit line BL4 receives noises .delta.R from both of the bit lines BL3 and BL5 via the coupling capacitance CBB between the bit lines. The magnitude .DELTA.VN of the noise can be approximately expressed as follows where the amplitude of readout data from a memory cell is VSO and the total capacitance of the bit line is CB. EQU .DELTA.VN=VSO.multidot.CBB/CB
Since the bit line BL4 is influenced by the bit lines BL3 and BL5 disposed on both sides thereof, independently it receives noises of 2.DELTA.VN in total.
Furthermore, in the writing or re-writing cycle, data is written in an order of (MC4 and MCS).fwdarw.(MC3 and MC7).fwdarw.(MC2 and MC6).fwdarw.(MC1 and MC5) as described before. When the operation of writing data into MC4 is completed, the transfer gate Q4 is made nonconductive. At this time, the potential of the word line WL1 is kept at the high voltage level in order to write data into MC3 or succeeding cells sequentially. After data of the memory cell MC4 is written, on the bit line BL4, BL4, to which MC4 is connected, is set in the electrically floating state.
Succeedingly, data is written into the memory cell MC3 through the bit line BL3, and a variation in the potential of the bit line BL3 in the writing operation is transmitted as noise .delta.W to the bit line BL4 via the capacitive coupling between the bit lines. The magnitude of the noise at this time is approximately equal to .DELTA.VN when it is expressed in terms of the magnitude of the noise which gives an influence on data at the time of reading.
When the writing operation is continuously effected and data is written into the cells MC1 and MC5, a variation in the potential of the bit line BL5 is also transmitted to the bit line BL4 as noise. After the operation of writing data into the cells MC1 and MC5 is completed, the potential of the word line WL1 is changed to a low voltage level. At this time, the potential of the cell MC4 is determined, but the potential equals to the potential of the bit line BL4 which is influenced by noise from the bit lines BL3 and BL5. Thus, also at the writing operation, it receives the noise of approx. 2.multidot..DELTA.VN.
As described above, the NAND type DRAM shown in FIGS. 6 and 7 receives the noise of approx. 2.multidot..DELTA.VN at the time of writing and the noise of approx. 2.multidot..DELTA.VN at the time of reading, and receives the noise of approx. 4.multidot..DELTA.VN=4.multidot.VSO.multidot.CBB/CB in total in the worst case. In a DRAM of 16 Mbit or more, CBB/CB exceeds 0.1. That is, most portion of a signal which can be originally derived from a memory cell could be lost by the noise, thereby significantly reducing the operation margin.
Thus, the conventional dynamic semiconductor memory device tends to be influenced by the interference noise between the bit lines at the time of writing/reading, causing the operation margin to be reduced.